FSM Project Status (10/07/2014 - 20:24:21)
Project File:	turn_signal.xise	Parser Errors:	No Errors
Module Name:	FSM	Implementation State:	Programming File Generated
Target Device:	xc3s500e-4fg320	Errors:	No Errors
Product Version:	ISE 14.6	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	36	9,312	1%
Number of 4 input LUTs	63	9,312	1%
Number of occupied Slices	52	4,656	1%
Number of Slices containing only related logic	52	52	100%
Number of Slices containing unrelated logic	0	52	0%
Total Number of 4 input LUTs	98	9,312	1%
Number used as logic	63
Number used as a route-thru	35
Number of bonded IOBs	6	232	2%
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	2.02

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Oct 7 20:16:48 2014	0	0	1 Info (1 new)
Translation Report	Current	Tue Oct 7 20:23:40 2014	0	0	0
Map Report	Current	Tue Oct 7 20:23:46 2014	0	0	2 Infos (2 new)
Place and Route Report	Current	Tue Oct 7 20:24:02 2014	0	0	2 Infos (2 new)
Power Report
Post-PAR Static Timing Report	Current	Tue Oct 7 20:24:06 2014	0	0	6 Infos (6 new)
Bitgen Report	Current	Tue Oct 7 20:24:12 2014	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Tue Oct 7 20:24:14 2014
WebTalk Log File	Current	Tue Oct 7 20:24:22 2014

Date Generated: 10/07/2014 - 20:24:22