Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: LIN64 Target Device: xc3s500e
Project ID (random number) 3d075b954a864c9e8678c31b9298be05.9F44150BE75B68B91718BC94069290B2.2 Target Package: fg320
Registration ID 210966754_0_0_158 Target Speed: -4
Date Generated 2014-11-03T21:59:01 Tool Flow ISE
 
User Environment
OS Name Arch OS Release Arch Linux
CPU Name Intel(R) Core(TM) i5-2500K CPU @ 3.30GHz CPU Speed 3540.667 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Registers=16
  • Flip-Flops=16
 Xors=8
  • 1-bit xor2=6
  • 8-bit xor2=2
 		MiscellaneousStatistics
  • AGG_BONDED_IO=35
  • AGG_IO=35
  • AGG_SLICE=17
  • NUM_4_INPUT_LUT=33
  • NUM_BONDED_IBUF=19
  • NUM_BONDED_IOB=16
  • NUM_SLICEL=17
  • NUM_SLICE_FF=16
 		NetStatistics
  • NumNets_Active=87
  • NumNodesOfType_Active_CLKPIN=8
  • NumNodesOfType_Active_DOUBLE=75
  • NumNodesOfType_Active_DUMMY=96
  • NumNodesOfType_Active_DUMMYESC=19
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_INPUT=112
  • NumNodesOfType_Active_IOBOUTPUT=19
  • NumNodesOfType_Active_OMUX=47
  • NumNodesOfType_Active_OUTPUT=33
  • NumNodesOfType_Active_PREBXBY=17
  • NumNodesOfType_Active_VFULLHEX=6
  • NumNodesOfType_Active_VLONG=2
  • NumNodesOfType_Active_VUNIHEX=16
 SiteStatistics
  • IBUF-DIFFM=6
  • IBUF-DIFFS=6
  • IOB-DIFFM=8
  • IOB-DIFFS=7
  • SLICEL-SLICEM=10
 		SiteSummary
  • IBUF=19
  • IBUF_INBUF=19
  • IBUF_PAD=19
  • IOB=16
  • IOB_OUTBUF=16
  • IOB_PAD=16
  • SLICEL=17
  • SLICEL_F=16
  • SLICEL_FFX=8
  • SLICEL_FFY=8
  • SLICEL_G=17
 
Configuration Data
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:19]
 IOB
  • O1=[O1_INV:0] [O1:16]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:16]
 IOB_PAD
  • DRIVEATTRBOX=[12:16]
  • IOATTRBOX=[LVCMOS25:16]
  • SLEW=[SLOW:16]
 SLICEL
  • CLK=[CLK:8] [CLK_INV:0]
 SLICEL_FFX
  • CK=[CK:8] [CK_INV:0]
  • D=[D:8] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:6] [INIT1:2]
  • FFX_SR_ATTR=[SRLOW:8]
  • LATCH_OR_FF=[FF:8]
  • SYNC_ATTR=[ASYNC:8]
 SLICEL_FFY
  • CK=[CK:8] [CK_INV:0]
  • D=[D:8] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:4] [INIT1:4]
  • FFY_SR_ATTR=[SRLOW:8]
  • LATCH_OR_FF=[FF:8]
  • SYNC_ATTR=[ASYNC:8]
 
Pin Data
IBUF
  • I=19
  • PAD=19
 IBUF_INBUF
  • IN=19
  • OUT=19
 IBUF_PAD
  • PAD=19
 IOB
  • O1=16
  • PAD=16
 IOB_OUTBUF
  • IN=16
  • OUT=16
 IOB_PAD
  • PAD=16
 SLICEL
  • CLK=8
  • F1=16
  • F2=16
  • F3=8
  • F4=4
  • G1=17
  • G2=17
  • G3=16
  • G4=2
  • X=8
  • XQ=8
  • Y=9
  • YQ=8
 SLICEL_F
  • A1=16
  • A2=16
  • A3=8
  • A4=4
  • D=16
 SLICEL_FFX
  • CK=8
  • D=8
  • Q=8
 SLICEL_FFY
  • CK=8
  • D=8
  • Q=8
 SLICEL_G
  • A1=17
  • A2=17
  • A3=16
  • A4=2
  • D=17
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 2 2 0 0 0 0 0
map 3 2 0 0 0 0 0
ngdbuild 3 3 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 2 2 0 0 0 0 0
xst 6 6 0 0 0 0 0
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Board=Spartan-3E Starter Board
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/encryptor_test PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2014-11-03T20:32:44 PROP_intWbtProjectID=9F44150BE75B68B91718BC94069290B2
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.encryptor_test
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=false
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s500e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_VHDL=3
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_FD=16 NGDBUILD_NUM_IBUF=19 NGDBUILD_NUM_LUT2=9 NGDBUILD_NUM_LUT3=18
NGDBUILD_NUM_LUT4=6 NGDBUILD_NUM_OBUF=16
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_FD=16 NGDBUILD_NUM_IBUF=19 NGDBUILD_NUM_LUT2=9 NGDBUILD_NUM_LUT3=18
NGDBUILD_NUM_LUT4=6 NGDBUILD_NUM_OBUF=16
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=940 ms, 660656 KB
Total Signals=32
Total Nets=77
Total Blocks=5
Total Processes=11
Total Simulation Time=1 us
Simulation Resource Usage=0.02 sec, 270434 KB
Simulation Mode=gui
Hardware CoSim=0